This invention relates to a semiconductor memory device that can carry out error detection and error correction with an error correcting code and to a method of testing the semiconductor memory device.
In a semiconductor memory device of the type described, data sets or words are kept on an array of memory cells in the form of either a pattern of charges stored therein or a voltage level distribution held therein. Each data set might fluctuate and cause an error to occur in the semiconductor memory device when each data set includes an undesirable noise. Such an error is called a soft error temporarily appearing in each data set and should be distinguished from a hard error indicative of a physical error.
In order to avoid an influence owing to such a soft error, it is known in the art to execute error correction which guarantees a proper data set free from an error when each data set is read out of the semiconductor memory device. The error correction is practically carried out with an error correction code written together with every one of data sets or word in the semiconductor memory device. More specifically, such a semiconductor memory device is operated in a write-in operation so that the error correction code is generated in response to each data set given as a write-in data set and is memorized in a memory section together with the write-in data set. In a readout operation, each data set is read out of the memory section to be decoded by the use of the corresponding error correction code into a readout data set. On decoding each data set read out of the memory section, an error is corrected by the use of the error correction code, if any. As a result, the readout data set which is subjected to error correction is produced from the semiconductor memory device.
To this end, the memory section in the semiconductor memory device has a data cell array and an error correction code cell array for memorizing the data sets and the corresponding error correction codes, respectively. In addition, the semiconductor memory device has an error correction code generator for generating an error correction code in response to each data set and a checking or decoding unit for decoding each data set read out of the memory section into the readout data set by the use of the error correction code.
Such a semiconductor memory device is very effective to read out a correct word even when a single error takes place in a memory cell. Herein, the above-mentioned write-in operation and readout operation will be collectively called a normal mode of operation for convenience of description.
In order to guarantee that such a normal mode is precisely executed, it has been considered that no hard error should be accepted and left in the memory section of the semiconductor memory device. Therefore, each of the data cell array and the error correction code cell array should be precisely tested so that no hard error is present in the data cell array and the error correction code cell array. For this purpose, each semiconductor memory device is usually checked by a test mode to guarantee absence of any hard error after it is manufactured. In other words, the semiconductor memory device is handled as an inferior product and is discarded. This results in a degradation of a yield of such a semiconductor memory device.
Under the above-mentioned consideration, disclosure is made in Japanese Unexamined Patent Publication No. Hei 5-54697, namely, 54697/1993 about testing such a semiconductor memory device which has a data cell array and an error correction code array. In the semi-conductor memory device, the data cell array and the error correction code array are individually controlled in the test mode to independently write a data set and an error correction code and to independently read them. Such independent write and read operation are helpful to detect whether or not each of the data cell array and the error correction code cell array is normal. Thus, the error correction code is very helpful to detect and correct each soft error in the semiconductor memory device.
However, the inventor has now been aware of the fact that occurrence of such a soft error is very rare or scarce in a recent semiconductor memory device due to development of a technique of preventing occurrence of such a soft error. This means that such an error correction code may not be always restricted to correction of only the soft error.
Under the circumstances, the above-referenced conventional testing method can not always effectively utilize an error correction code to test such a semiconductor memory device which hardly causes an error to occur. This is because the above-referenced conventional testing method is used only on a precondition that only the soft error is corrected by such an error correction code and besides, the precondition for the above testing method is remote from and is not matched with an actual situation.